1. Field of Invention
The present invention relates to an electro-optic apparatus, a driving method for the same, and an electronic appliance.
2. Description of Related Art
Among related art electric optical apparatus, such as liquid crystal display apparatus, apparatus equipped with memories in each pixel to reduce power consumption are disclosed in Japanese Unexamined Patent Publication No. H08-286170 (FIG. 10).
FIG. 8 is a circuit schematic showing one example of such a liquid crystal display apparatus. FIG. 9 is a timing chart showing how the same apparatus is driven. As shown in FIG. 8, this liquid crystal display apparatus is equipped with a plurality of scan line pairs Yai, Ybi (where i is a natural number in a range of 1 to n) and a plurality of data lines Xj (where j is a natural number in a range of 1 to m) that intersect the scan line pairs. Respective pixels Pij are formed corresponding to intersections between the respective scan line pairs Yai, Ybi and the data lines Xj.
In each pixel Pij, a liquid crystal capacitive element 93 is formed by sandwiching liquid crystals between a pixel electrode 91 and a counter electrode 92 that is supplied with a counter electrode signal COM commonly supplied to every pixel. Each pixel Pij also includes an analog switch 94, a latch circuit 95, and a read circuit 96. The data line Xj is connected via the analog switch 94, the latch circuit 95, and the read circuit 96 to the pixel electrode 91.
The analog switch 94 is connected to the scan line pair Yai, Ybi and is turned on when a scan signal WRT at a high level is supplied on one signal line out of the pair, the signal line Yai, and an inverted signal WRTX of the scan signal WRT at a low level is simultaneously supplied on the other signal line, the signal line Ybi. As a result, logic that corresponds to a tone is read into pixel electrode 91 via the data line Xj.
The latch circuit 95 is composed of two inverters 95a, 95b and is supplied with power via two (i.e., plus and minus) power supply lines 97a, 98b. When logic is read and the analog switch 94 has then been turned off, the latch circuit 95 thereafter holds the logic at that time.
The read circuit 96 is composed of an N-channel TFT 96a and a P-channel TFT 96b. The respective drains of the TFTs are connected to the pixel electrode 91. The source of the N-channel TFT 96a is connected to the output terminal of the inverter 95b, while the source of the P-channel TFT 96b is connected to the output terminal of the inverter 95a. The respective gates of the TFTs are connected to a polarity line 98. A polarity signal POL that cyclically inverts the polarity is supplied via the polarity line 98. Accordingly, one of the N-channel TFT 96a and the P-channel TFT 96b is turned ON according to the level (polarity) of the polarity signal (POL) supplied to the polarity line 98. Specifically, in a state where logic is stored by the latch circuit 95, when the polarity signal POL is at a high level, the N-channel TFT 96a is turned ON and the logic outputted from the inverter 95b is outputted to the pixel electrode 91.
When the polarity signal POL is at a low level, the P-channel TFT 96b is turned ON and the logic output from the inverter 95a is output to the pixel electrode 91. In this way, logic, or the inverse of such logic, is applied to the pixel electrode 91 during a read according to the level of the polarity signal POL supplied to the polarity line 98 so that the electric field applied to the liquid crystals is switched to drive the liquid crystals with an alternating current (AC).
The operation during the driving of the respective pixels in this kind of construction is described below with reference to FIG. 9. It should be noted that when the polarity signal POL is at the high level, the logic read into the pixel electrode 91 has a potential VDD for a display of black and a potential VSS (<VDD) for a display of white. Similarly, when the polarity signal POL is at the low level, the logic read into the pixel electrode 91 has the potential VSS for a display of black and the potential VDD for a display of white.
The respective power supply voltages supplied to the latch circuit 95 via the power supply lines 97a, 97b are set at the potentials VDD and VSS. Accordingly, the logic held in the latch circuit 95 has the respective potentials VDD and VSS at the high level and the low level. The latch circuit 95 (the inverters 95a, 95b) outputs the potential VDD that is the high level and the potential VSS that is the low level corresponding to the held logic to the read circuit 96.
When the polarity signal POL is at the high level, the latch circuit 95 outputs, via the N-channel TFT 96a, the high-level potential VDD for displaying black to the pixel electrode 91 or the low-level potential VSS for displaying white to the pixel electrode 91. After this, when the polarity signal POL switches to the low level with the same logic being held, the latch circuit 95 outputs, via the P-channel TFT 96b, the low-level potential VSS for displaying black to the pixel electrode 91 or the high-level potential VDD for displaying white to the pixel electrode 91. This is also the case when the polarity signal POL switches from the low level to the high level.
Here, the potential of the counter electrode signal COM supplied to the counter electrode 92 also undergoes a transition corresponding to the level of the polarity signal POL. When the electrode signal POL is at the high level, the counter electrode signal COM is set at a predetermined potential Vm that is lower than the potential VSS. When the electrode signal POL is at the low level, the counter electrode signal COM is set at a predetermined potential Vp that is higher than the potential VDD. The potential of the counter electrode signal COM has to be cyclically inverted in accordance with the polarity signal POL in this way since the latch circuit 95 is only capable of assuming two kinds of logic (levels) during AC driving of the liquid crystals.
By doing so, during a display of black, when the polarity signal POL is at the high level, a voltage (VDD-Vm) is applied between the pixel electrode 91 and the counter electrode 92. When the polarity signal POL is at the low level, a voltage (Vp-VSS) is applied between the pixel electrode 91 and the counter electrode 92. In the same way, during a display of white, when the polarity signal POL is at the high level, a voltage (VSS-Vm) is applied between the pixel electrode 91 and the counter electrode 92. When the polarity signal POL is at the low level, a voltage (Vp-VDD) is applied between the pixel electrode 91 and the counter electrode 92. By doing so, a tone is held by the pixel Pij while the liquid crystals are driven with AC.